Senior Engineer, Device Modeling

Job Description

Senior Engineer, Device Modeling
Location:

San Diego, CA, US

pSemi Corporation is a Murata company driving semiconductor integration. pSemi builds on Peregrine Semiconductor's 30-year legacy of technology advancements and strong IP portfolio but with a new mission-to enhance Murata's world-class capabilities with high-performance semiconductors. With a strong foundation in RF integration, pSemi's product portfolio now spans power management, connected sensors, optical transceivers, antenna tuning and RF frontends. These intelligent and efficient semiconductors enable advanced modules for smartphones, base stations, personal computers, electric vehicles, data centers, IoT devices and healthcare. From headquarters in San Diego and offices around the world, pSemi's team explores new ways to make electronics for the connected world smaller, thinner, faster and better.

Senior Engineer, Device Modeling

Job Duties: Modeling development of pSemi's patented high-performance UltraCMOS technology. Work with modeling engineers and CAD to support internal design groups and external foundry customers in device measurements and data analysis. Methodology development for EM model extraction of packages and passives. Detailed analysis of characterization data. Provide technical insight and support to the design teams. Design Modeling DC and RF test structures for on-wafer characterization. Mentor junior engineers and providing guidance to design teams in their area of expertise.

Required education: Master of Science or equivalent in Electrical Engineering, Electronic Engineering, or related.

Required experience: 12 months as Senior Engineer, Device Modeling, or RF and Antenna Engineer, or Senior RF Hardware Engineer.

Additional minimum requirements: work experience to include at least 12 months with the following:
1. Advance Electromagnetic theory and complex material properties.
2. Design of experiment for EM analysis, modeling the impact of EM fields on the performance of integrated circuits.
3. Layout optimization for RFIC design, taking RF data and creating lump element models;
4. Common EM EDA tools including HFSS.
40 hours/ week. Job site/ interview: San Diego, CA. EOE

USD 115000 - 125000 per year


pSemi Corporation supports a diverse workforce and is committed to a policy of equal employment opportunity for applicants and employees. pSemi does not discriminate on the basis of age, race, color, religion (including religious dress and grooming practices), sex/gender (including pregnancy, childbirth, or related medical conditions or breastfeeding), gender identity, gender expression, genetic information, national origin (including language use restrictions and possession of a driver's license issued under Vehicle Code section 12801.9), ancestry, physical or mental disability, legally-protected medical condition, military or veteran status (including "protected veterans" under applicable affirmative action laws), marital status, sexual orientation, or any other basis protected by local, state or federal laws applicable to the Company. pSemi also prohibits discrimination based on the perception that an employee or applicant has any of those characteristics, or is associated with a person who has or is perceived as having any of those characteristics.

Note: The Peregrine Semiconductor name, Peregrine Semiconductor logoand UltraCMOS are registered trademarks and the pSemi name, pSemi logo, HaRP andDuNE are trademarks of pSemi Corporation in the U.S. and other countries. All other trademarks are the property of their respective companies. pSemi products are protected under one or more of the following U.S. Patents: http://patents.psemi.com

Additional Position Information:


Nearest Major Market: San Diego

 

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